(Hong Kong)
Product Summary
The GAL20V8B-25QP is a High Performance E2CMOS PLD. The device combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the GAL20V8B-25QP to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20V8B-25QP are the PAL architectures. The device is capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility.
Parametrics
GAL20V8B-25QP absolute maximum ratings: (1)Supply voltage VCC: –0.5 to +7V; (2)Input voltage applied: –2.5 to VCC +1.0V; (3)Off-state output voltage applied: –2.5 to VCC +1.0V; (4)Storage Temperature: –65 to 150℃; (5)Ambient Temperature with Power Applied: –55 to 125℃.
Features
GAL20V8B-25QP features: (1)5 ns Maximum Propagation Delay; (2)Fmax = 166 MHz; (3)4 ns Maximum from Clock Input to Data Output; (4)UltraMOS Advanced CMOS Technology; (5)E2 CELL TECHNOLOGY; (6)Reconfigurable Logic; (7)Reprogrammable Cells; (8)100% Tested/100% Yields; (9)High Speed Electrical Erasure (<100ms); (10)20 Year Data Retention; (11)Maximum Flexibility for Complex Logic Designs; (12)Programmable Output Polarity; (13)Also Emulates 24-pin PAL Devices with Full Function/Fuse Map/Parametric Compatibility; (14)PRELOAD AND POWER-ON RESET OF ALL REGISTERS: 100% Functional Testability; (15)active pull-ups on all pins.
Diagrams
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 GAL20V8B-25QP |
Lattice |
SPLD - Simple Programmable Logic Devices 5V 20 I/O |
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GAL20V8B-25QPI |
Lattice |
SPLD - Simple Programmable Logic Devices HI PERF E2CMOS PLD |
Data Sheet |
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GAL20V8B-25QPN |
Lattice |
SPLD - Simple Programmable Logic Devices 5V 20 I/O |
Data Sheet |
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GAL20V8B-25QPNI |
Lattice |
SPLD - Simple Programmable Logic Devices HI PERF E2CMOS PLD |
Data Sheet |
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