(Hong Kong)
Product Summary
The DSP56002FC40 is a MPU-style general purpose Digital Signal Processor (DSP) composed of an efficient 24-bit DSP core, program and data memories, various peripherals, and support circuitry. The DSP56002FC40 core is fed by on-chip Program RAM, and two independent data RAMs. The device contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI), parallel Host Interface (HI), Timer/Event Counter, Phase Lock Loop (PLL), and an On-Chip Emulation (OnCE) port.
Parametrics
Absolute maximum ratings (GND = 0 V): (1)Supply Voltage, VCC: –0.3 to +7.0 V; (2)All Input Voltages, VIN: (GND – 0.5) to (VCC + 0.5) V; (3)Current Drain per Pin excluding VCC and GND, I: 10 mA; (4)Operating Temperature Range, TJ: –40 to +105℃; (5)Storage Temperature, Tstg: –55 to +150℃(6)Double precision 48×48-bit multiply with 96-bit result in 6 instruction cycles.
Features
Features: (1)Efficient 24-bit DSP56000 core; (2)Up to 40 Million Instructions Per Second (MIPS), 25 ns instruction cycle at 80 MHz; up to 33 MIPS, 30.3 ns instruction cycle at 66 MHz; (3)Up to 240 Million Operations Per Second (MOPS) at 80 MHz; up to 198 MOPS at 66 MHz; (4)Performs a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks; (5)Highly parallel instruction set with unique DSP addressing modes; (6)Two 56-bit accumulators including extension bits; (7)Parallel 24×24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles); (8)Double precision 48×48-bit multiply with 96-bit result in 6 instruction cycles; (9)56-bit addition/subtraction in 1 instruction cycle; (10)Fractional and integer arithmetic with support for multiprecision arithmetic; (11)Hardware support for block-floating point FFT; (12)Hardware nested DO loops; (13)Zero-overhead fast interrupts (2 instruction cycles); (14)Four 24-bit internal data buses and three 16-bit internal address buses for maximum information transfer on-chip.
Diagrams
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 DSP56001 |
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DSP56001A |
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DSP56002 |
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DSP56004 |
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DSP56005 |
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DSP56007 |
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Negotiable |
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